Digital signals are commonly coupled to and from electronic devices, such as memory devices, at a high rate of speed. The Digital signals are normally coupled to an input buffer or receiver, which generates a digital signal corresponding to the Digital signal applied to the input of the receiver. The timing at which the signal at the output of the receiver changes state is often critically important for timing the relationships within the electronic device. In particular, it is important that the transition of the digital signal not become skewed relative to other digital signals in the electronic device. The difficulty of avoiding signal skew is increased when the digital signals applied to input receivers switch between two voltages that are relatively close to each other.
One technique for preventing the timing of digital signals becoming skewed is to use differential signals, which tend to avoid skewing because of their inherent symmetry even where the voltage between which the signals transition is relatively small. However, some memory bus signaling protocols do not couple differential signals to memory devices. In these devices, the input signal must be compared to a reference voltage to determine the trip point of the receivers. More specifically, when the magnitude of the input signal is greater than the reference voltage, the output of the receiver has a first binary value. When the magnitude of the input signal is less than a reference voltage, the output of the receiver has a second binary value. Ideally, the reference voltage is centered between the two voltages between which the input signal transitions. However, because the input signal may lack symmetry, the ideal reference voltage may be at some other level. In either case, the use of a reference voltage can allow the input receivers to accurately convert digital signals switching within a relatively small voltage range to a receiver output signal that switches within a substantially larger voltage range.
Reference voltages for input receivers are traditionally generated at a single source, and then distributed to each of the input receivers. Distributing the reference voltage in this manner can create a number of problems, all of which can skew the signals generated at the output of the input receivers. For example, noise signals can be coupled to input signal lines from various sources, such as power supply noise and switching noise, may alter the voltages between which the input signal switches. As a result, the reference voltage may no longer be centered between the voltages between which the input signal switches. Furthermore, a lack of symmetry in the input signal can alter the ideal value of the reference voltage. As a result, the signal at the output of the receiver may be skewed, which can lead to degraded timing margins within the memory device.
Not only is it possible for timing skew to result from noise signals to the input signal lines, but timing skew can also result from noise signals coupled to reference voltage distribution lines. The susceptibility of noise signals being coupled to reference voltage distribution lines is exacerbated by the widespread routing of such lines to sometimes hundreds of input receivers at various locations throughout the memory device. Noise can be coupled to these distribution lines through various mechanisms, such as power supply coupling through decoupling capacitors connected to the voltage reference distribution lines. The noise signals can significantly alter the reference voltage at various input receivers thereby altering the voltage of the input signal at which the output of the input receiver switches. The result is a skewing of the output signal, which, as mentioned above, can adversely affect timing relationships within the memory device. Under the circumstances, it may not be possible for the memory device to function properly at high operating speeds.
There is therefore a need for a method and system for generating a reference voltage having an optimum magnitude and for maintaining the reference voltage at that value at the input of each of many input receivers.